create_clock -period 12.500 -name clk_input -waveform {0.000 6.250} [get_nets *clk*]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[15]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[14]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[13]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[12]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {bmg_out[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[32]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[31]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[30]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[29]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[28]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[27]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[26]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[25]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[24]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[23]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[22]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[21]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[20]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[19]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[18]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[17]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[16]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[15]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[14]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[13]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[12]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[11]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[10]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fir_hdl_out[0]}]

